ADP5042
Data Sheet
Rev. A | Page 24 of 32
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
(
)
OUT
SW
IN
RIPPLE
C
L
f
V
V
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
2
2?/DIV>
OUT
SW
RIPPLE
C
f
I
?/DIV>
?/DIV>
8
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
IPPLE
RIPPLE
COUT
I
V
ESR
d
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 礔 and a
maximum of 40 礔.
Table 12. Suggested 10 糉 Capacitors
Vendor
Type Model
Case
Size
Voltage
Rating (V)
Murata
X5R
GRM188R60J106 0603 6.3
Taiyo Yuden X5R
JMK107BJ475
0603 6.3
TDK
X5R
C1608JB0J106K
0603 6.3
Panasonic
X5R
ECJ1VB0J106M
0603 6.3
The buck regulator requires 10 礔 output capacitors to guaran-
tee stability and response to rapid load variations and to transition
in and out the PWM/PSM modes. In certain applications, where
the buck regulator powers a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 礔 to 4.7 礔 because the regulator does not expect a
large load variation when working in PSM mode (see Figure 62).
SW
VIN1
VIN2
VIN3
VOUT1
VOUT2
nRSTO
PGND
VOUT3
L1
1礖
C6
4.7礔
C4
1礔
R1
100k&
C5
1礔
C2
4.7礔
C1
1礔
C3
1礔
AVIN
R
FLT
30&
V
IN
.3V TO 5.5V
MICRO PMU
ADP5042
PROCESSOR
ANALOG
SUB-SYSTEM
VCORE
VDDIO
RESET
GPIO1
MODE
WDI
GPIO2
ENx
GPIO[x:y]
VANA
3
Figure 62. Processor System Power Management with PSM/PWM Control
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
IN
OUT
IN
OUT
MAX
LOAD
CIN
V
V
V
V
I
I
)
(
)
(
e
To minimize supply noise, place the input capacitor as close
to the VIN pin of the buck as possible. As with the output
capacitor, a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 礔 and a
maximum of 10 礔. A list of suggested capacitors is shown in
Table 13.
Table 13. Suggested 4.7 糉 Capacitors
Vendor
Type Model
Case
Size
Voltage
Rating
(V)
Murata
X5R
GRM188R60J475ME19D 0603 6.3
Taiyo Yuden X5R
JMK107BJ475
0603 6.3
Panasonic
X5R
ECJ-0EB0J475M
0402 6.3
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5042 LDOs are designed for operation with small,
space-saving ceramic capacitors, but they function with most
commonly used capacitors as long as care is taken with the ESR
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 礔 capacitance with an
ESR of 1 & or less is recommended to ensure stability of the
ADP5042. Transient response to changes in load current is also
affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP5042 to
large changes in load current.
Input Bypass Capacitor
Connecting a 1 礔 capacitor from VIN2 and VIN3 to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance is encountered. If greater than 1 礔 of output
capacitance is required, increase the input capacitor to match it.
Table 14. Suggested 1.0 糉 Capacitors
Vendor
Type Model
Case
Size
Voltage
Rating
(V)
Murata
X5R GRM155R61A105ME15 0402 10.0
TDK
X5R
C1005JB0J105KT
0402 6.3
Panasonic
X5R
ECJ0EB0J105K
0402 6.3
Taiyo Yuden X5R
LMK105BJ105MV-F
0402 10.0
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